1. Field of the Invention
Apparatuses and methods consistent with the present invention relate to data processing for a flash memory, and more particularly, to data processing for a flash memory which makes it easy to determine whether data stored in the flash memory is valid.
2. Description of the Related Art
In general, home appliances, communications devices, and embedded systems, such as set-top boxes, use non-volatile memories as storage devices for storing and processing data.
Flash memories are a type of non-volatile memory, in which data can be electrically erased and overwritten. Flash memories are suitable for portable devices because they consume less power than magnetic disc memory-based storage mediums, are as accessible as hard discs, and are compact-sized.
In the flash memory, when new data is overwritten on pre-written data, a process of erasing the whole block, in which the pre-written data is stored, is required due to a hardware characteristic of the flash memory.
In order to prevent performance deterioration of the flash memory, which may occur due to discordance between a data writing unit and a data erasure unit in the flash memory, concepts of a logical address and a physical address are introduced.
Herein, the logical address is an address used when a user requests a data operation, such as data reading, data writing, etc., in the flash memory through a predetermined user program, and the physical address is an address used when the flash memory actually performs the data operation, such as data reading, data writing, etc.
In addition, a flash memory is classified into a small-block flash memory or a large-block flash memory. In a small-block flash memory, a logical operation unit is identical to a physical operation unit, while in a large-block flash memory, a physical operation unit is larger than a logical operation unit.
FIG. 1A is a diagram illustrating the structure of a typical small-block flash memory, and FIG. 1B is a diagram illustrating the structure of a typical large-block flash memory.
Referring to FIG. 1A, a sector 11 which is a logical operation unit of a small-block flash memory constitutes a page 12 which is a physical operation unit of the small-block flash memory.
In other words, the logical operation unit of the small-block flash memory is the same as the physical operation unit of the small-block flash memory. On the other hand, referring to FIG. 1B, at least one sector 21 which is a logical operation unit of a large-block flash memory constitutes a page 22 which is a physical operation unit of the large-block flash memory.
A flash memory-based system may unexpectedly suffer from frequent power interruptions due to its characteristics. Therefore, the flash memory-based system needs a function of recovering data damaged or lost due to a power interruption.
In detail, the operations of writing data to and reading data from a flash memory will now be described in detail. If power is cut off in the process of writing data to a flash memory, only part of the data is successfully written to the flash memory. Meanwhile, if power is cut off in the process of erasing data from a flash memory, only part of the data is successfully erased from the flash memory.
Therefore, a variety of methods of determining whether data stored in a flash memory is valid if power is cut off before completing the process of performing a data operation, such as a write operation or an erase operation, on the flash memory have been suggested.
Conventionally, error correction code (ECC) has been widely used to determine whether data stored in a flash memory is valid when an unexpected event, such as a power outage or write disturbance, occurs. ECC may detect and correct errors therein as well as errors in other data.
In detail, referring to FIG. 2, a flash memory comprises a block 34, and the block 34 comprises a plurality of pages 33 each consisting of a data region 31 and an ECC region 32.
One-bit errors are likely to occur in a flash memory. ECC can detect and correct one-bit errors and detect, but not correct, two-bit to (m−1)-bit errors. It is yet to be known whether ECC can be adapted to detect and correct errors of m bits or more. In other words, ECC may not be able to detect or correct errors of m bits or more properly. Therefore, ECC is written to a flash memory when performing a data operation on the flash memory, and thus, when error occurs in the flash memory due to an unexpected event, such as a power outage, the error can be detected and/or corrected using the ECC.
FIG. 3 is a flowchart illustrating a conventional method of detecting and correcting errors using ECC.
Referring to FIG. 3, in operation S10, data and ECC are extracted from a flash memory.
In operation S20, ECC is generated based on the extracted data obtained in operation S10. The generated ECC is based on the same algorithm as the extracted ECC.
In operation S30, it is determined whether the generated ECC matches the extracted ECC. If it is determined in operation S20 that the generated ECC does not match the extracted ECC, error detection is performed on the extracted data and the extracted ECC.
It is assumed that ECC can detect and correct one-bit errors and can detect but not correct two-bit errors and that it is not certain whether ECC is able to detect and correct errors of three or more bits, and thus there is a possibility of ECC correcting errors of three or more bits improperly.
If a one-bit error is detected from the extracted data and the extracted ECC in operation S40, error correction is carried out on the one-bit error in operation S50. Thereafter, in operation S60, the extracted data is determined as being valid.
In operation S70, if a two-bit error is detected from the extracted data and the extracted ECC, an error occurrence message is created. Since ECC cannot correct but can detect a two-bit error, the extracted data is determined as being invalid in operation S80.
If it is determined in operation S30 that the generated ECC matches the extracted ECC, the extracted data is determined as being valid in operation S60.
At this time, if a three-bit error is detected from the extracted data and the extracted ECC, for example, if a one-bit error is detected from the extracted data and a two-bit error is detected from the extracted ECC, the three-bit error may be improperly corrected, in which case, however, the extracted data is mistakenly determined as being valid even though it is not.
In detail, if 3 erroneous bits are detected from a flash memory, one from a data region 31 of a flash memory where data exists and the other two from an ECC region 32 of the flash memory, as illustrated in FIG. 4A, ECC may mistakenly correct a bit other than the erroneous bit detected from the data region 31, as illustrated in FIG. 4B. Therefore, there has been a need to minimize the possibility of improper error correction when three or more erroneous bits are simultaneously detected from a flash memory.
Japanese Patent Laid-Open Publication No. 1999-016389 discloses a semiconductor memory device which stores a data signal, a parity signal, and an inverted parity signal together. However, the semiconductor memory device is not able to correct greater than three erroneous bits of a flash memory.
Accordingly, there still exists a need for ECC processing of three or more erroneous bits.